Asymmetric multiprocessing
Asymmetric multiprocessing, or AMP, was a software stopgap for handling multiple CPUs before symmetric multiprocessing, or SMP, was available.
Multiprocessing is the use of more than one CPU in a computer system. The CPU is the arithmetic and logic engine that executes user applications; an I/O interface such as a GPU, even if it is implemented using an embedded processor, does not constitute a CPU because it does not run the user's application program. With multiple CPUs, more than one set of program instructions can be executed at the same time. All of the CPUs have the same user-mode instruction set, so a running job can be rescheduled from one CPU to another.[1]
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Background and history
For the room-size computers of the 1960s and 1970s, a cost-effective way to increase compute power was to add a second CPU. Since these computers were already close to the fastest available (near the peak of the price:performance ratio), two standard-speed CPUs were much less expensive than a CPU that ran twice as fast. Also, adding a second CPU was less expensive than a second complete computer, which would need its own peripherals, thus requiring much more floor space and an increased operations staff.
Notable early offerings by computer manufacturers were the Burroughs B5000, the DECsystem-1055, and the IBM System/360 model 65MP. There were also dual-CPU machines built at universities.[2]
The problem with adding a second CPU to a computer system was that the operating system had been developed for single-CPU systems, and extending it to handle multiple CPUs efficiently and reliably took a long time. To fill the gap, operating systems intended for single CPUs were initially extended to provide minimal support for a second CPU. In this minimal support, the operating system ran on the “boot” processor, with the other only allowed to run user programs. The next step towards symmetric multiprocessing (SMP) was to allow the operating system to run on any CPU, but only on one at a time, which could be thought of as a form of symmetric multiprocessing with a single coarse-grained lock. Eventually the operating systems improved their method of using the additional CPUs until they achieved full SMP, in which the operating system and the applications under its control ran on all of the CPUs simultaneously, with finer-grained locking.
Burroughs B5000[3]
An option on the Burroughs B5000 was “Processor B”. This second processor, unlike “Processor A” had no connection to the peripherals, though the two processors shared main memory. The operating system ran only on Processor A. When there was a user job to be executed, it might be run on Processor B, but when that job tried to access the operating system the processor halted and signaled Processor A. The requested operating system service was then run on Processor A.[4]
IBM System/360 models 65MP[5] and 67-2[6]
IBM offered dual-processor computer systems based on its System/360 model 65 and the closely related model 67. The operating systems which ran on these machines were OS/360 M65MP[7] and TSS/360. There was also software developed at universities which used both CPUs, notably MTS. Both processors had access to the data channels, and so could initiate I/O.
M65MP was closer to SMP than MCP for the B5000 or TOPS-10 for the DECsystem-1055, since the operating system kernel ran on both processors (though with a “big lock” around the I/O handler) and peripherals could generally be attached to either processor.[8]
The MTS supervisor (UMMPS) ran on either or both CPUs of the IBM System/360 model 67-2. Supervisor locks were small and were used to protect individual common data structures that might be accessed simultaneously from either CPU. As with M65MP, Individual tasks (jobs, processes) would only execute on one processor at a time.[9]
CDC 6500[10] and 6700
Control Data Corporation offered two configurations of its CDC 6000 series that featured two processors. The CDC 6500 was a CDC 6400 with two processors. The CDC 6700 was a CDC 6600 with the CDC 6400 processor added to it.
These systems were organized quite differently from the other multiprocessors in this article. The operating system ran on the peripheral processors, while the user's application ran on the CPUs. Thus, the terms ASMP and SMP do not properly apply to these multiprocessors.
DECsystem-1055[11]
Digital Equipment Corporation offered a dual-processor version of its DECsystem-1050 which used two KA10 processors.[12] This offering was extended to later processors in the PDP-10 line. DEC also had a multi-processor PDP-11[13] and several multi-processor VAX systems.[14][15]
Univac 1108-II[16]
The Univac 1108-II and its successors had up to three CPUs.[17] These computers ran the UNIVAC EXEC 8 operating system, but it is not clear from the surviving documentation where that operating system was on the path from asymmetric to symmetric multiprocessing.
Multics
Multics ran on several computers between 1964 and 2000, including some multiprocessors. Details are scarce, but it appears that Multics would today be called an asymmetric multiprocessing system, because a user program could run on only one CPU.[18]
IBM System/370 model 168[19]
Two options were available for the IBM System/370 model 168 for attaching a second processor. One was the IBM 3062 Attached Processing Unit, in which the second processor had no access to the channels, and was therefore similar to the B5000's Processor B or the second processor on a VAX-11/782. The other option offered a complete second CPU, and was thus more like the System/360 model 65MP.
See also
- 3B20C
- Multi-core (computing)
- Software lockout
- Giant lock
- Symmetric multiprocessing
- Heterogeneous computing
Notes
- ^ Introduction to Multiprocessing: distinguishes “symmetric” from “master/slave”
- ^ Early Computers at Stanford: the dual processor computer at the AI lab
- ^ Operational Characteristics of the Processors for the Burroughs B5000
- ^ A Narrative Description of the B5500 MCP, pages 29 (initiate routine) and 40 (a note on parallel processing)
- ^ IBM (September 1968), IBM System/360 Model 65 Functional Characteristics, Fourth Edition, A22-6884-3, http://www.bitsavers.org/pdf/ibm/360/funcChar/A22-6884-3_360-65_funcChar.pdf.
- ^ IBM (February, 1972), IBM System/360 Model 67 Functional Characteristics, Third Edition, GA27-2719-2, http://www.bitsavers.org/pdf/ibm/360/funcChar/GA27-2719-2_360-67_funcChar.pdf.
- ^ M65MP: An Experiment in OS/360 multiprocessing
- ^ IBM, "OS I/O Supervisor PLM" - GY28-6616-9, Program Logic Manual, R21.7, April 1973
- ^ Time Sharing Supervisor Programs by Mike Alexander (May 1971) has information on MTS, TSS, CP/67, and Multics
- ^ CONTROL DATA 6400/6500/6600 COMPUTER SYSTEMS Reference Manual
- ^ Introduction to DECsystem-10 Software, section 1.4 (DECsystem-10 Multiprocessing)
- ^ DECsystem-10 Technical Summary page 2-1
- ^ RSX-11M multiprocessing
- ^ VAX Product Sales Guide, pages 1-23 and 1-24: the VAX-11/782 is described as an asymmetric multiprocessing system in 1982
- ^ VAX 8820/8830/8840 System Hardware User's Guide: by 1988 the VAX operating system was SMP
- ^ Univac 1108-II announcement
- ^ A history of Univac computers and Operating Systems
- ^ Multics execution environment, section 6.11.5 Multiprocessing
- ^ IBM (January 1976), IBM System/370 Model 168 Functional Characteristics, Fifth Edition, GA22·7010-4, http://www.bitsavers.org/pdf/ibm/370/funcChar/GA22-7010-4_370-168_funcChar_Jul76.pdf.
References
- Bell, C. Gordon, Mudge, J. Craig, McNamara John E. "The PDP-10 Family". (1979). Part V of Computer Engineering: A DEC View of Hardware Systems Design. Digital Equipment Corp.
- Rajkumar Buyya (editor): High Performance Cluster Computing: Architectures and Systems, Volume 1, ISBN 0-13-013784-7, Prentice Hall, NJ, USA, 1999.
- Rajkumar Buyya (editor): High Performance Cluster Computing: Programming and Applications, Volume 2, ISBN 0-13-013785-5, Prentice Hall, NJ, USA, 1999.
External links
- OpenMP tutorial for parallel programming
- Enea OSE
- History of Multi-Processing
- Linux and Multiprocessing
- ASOSI: Asymmetric Operating System Infrastructure, Proc. 21st Conference on Parallel and Distributed Computing and Communication Systems, (PDCCS 2008), New Orleans, Louisiana, pp. 193-198, 2008
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